1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and in particular, to a structure of a gate insulating film and an inter-gate insulating film in a memory cell.
2. Description of the Related Art
Nonvolatile semiconductor memories, for example, flash memories, are mounted in various electronic apparatuses. Memory cells in a flash memory each have a gate electrode structure in which a charge storage layer and a control gate electrode are stacked on a gate insulating film (tunnel insulating film) on a surface of a semiconductor substrate (channel region) via an inter-gate insulating film.
In the memory cell configured as described above, for example, a thermal oxide film of thickness approximate 8 nm is used as a gate insulating film. A laminated film (ONO film) of thickness approximate 15 nm made up of a silicon oxide film, a silicon nitride film, and a silicon oxide film as an inter-gate insulating film. A floating gate electrode made up of polycrystalline silicon is used as a charge storage layer. A top surface of the floating gate electrode and side surfaces of the floating gate electrode in a channel width direction are covered with the control gate electrode via the inter-gate insulating film. Thus, the opposed area between the floating gate and the control gate is increased to ensure a proper coupling ratio of the memory cell.
Efforts have been made to miniaturize memory cells to increase memory capacity. There has been a demand for a reduction in a write/erase voltage of the memory cell. However, when an attempt is made to reduce the thickness of a tunnel insulating film and thus an operating voltage, leakage characteristics of the tunnel insulating film at a low electric field may disadvantageously be degraded. As a result, data retention characteristics of the memory cell may be degraded.
An effective alternative method for reducing the write/erase voltage is to increase the coupling ratio. However, the reduced thickness of the inter-gate insulating film may degrade the leakage characteristics of the inter-gate insulating film. Thus, as is the case with the reduced thickness of the tunnel insulating film, the data retention characteristics of the memory cell may be degraded.
When the miniaturized memory cell prevents the side surfaces of the floating gate electrode from being covered with the control gate electrode, the control gate electrode can contact the floating gate electrode only at the top surface. This reduces the coupling ratio. Similarly, if an insulating film with a high trap level, such as a silicon nitride film, is used as a charge storage layer, as in the case of metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells, the coupling ratio is low because the control gate electrode contacts the charge storage layer (silicon nitride film) at the top surface.
Disadvantageously, the reduced coupling ratio of the memory cell increases the write/erase voltage, and when an attempt is made to solve this problem by reducing the thicknesses of the tunnel insulating film and the block insulating film, the data retention characteristics of the memory cell may be degraded as described above.
Jpn. Pat. Appln. KOKAI Publication No. 2003-188356 discloses a technique intended mainly to improve the data retention characteristics of MFMIS memory cells utilizing polarization of a ferroelectric substance and in which a gate insulating film in the memory cell has a two-layer structure made up of a high-dielectric film and a tunnel insulating film to inhibit a possible leakage current and to improve charge retention characteristics. Jpn. Pat. Appln. KOKAI Publication No. 2007-12922 discloses a structure in which a gate insulating film in a memory cell is made up of the gate insulating film on a surface of a semiconductor substrate and a very thin high-dielectric film on the gate insulating film.